1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method for forming a metal line in a semiconductor device, which can effectively suppress abnormal oxidation in formation of metal line of tungsten or tungsten silicide.
2. Background of the Related Art
Keeping pace with the trend of highly integrating semiconductor devices, drop of device operation speed has been resulting, not only in the case of metal line, but also in the cases of gate line and bit line. That is, a reduction of line width increases resistance, and the increased resistance causes RC delay time periods, to act as a main cause to deteriorate device performances, at the end. In order to solve the problem of increased resistivity, formation of the gate line or bit line of tungsten or tungsten silicide is suggested. That is, it is intended that a refractory metal silicide, such as tungsten silicide (WSix), titanium silicide (TiSi2), or cobalt silicide (CoSi2), is formed on the polysilicon layer for solving the problem of the increased resistivity of the metal line.
A related art process for forming a metal line in a semiconductor device will be explained with reference to the attached drawing. FIG. 1 illustrates a related art process for forming a metal line, and FIGS. 2a.about.2e illustrate sections showing the steps of a related art process for forming a metal line.
The related art process for forming a metal line of tungsten or tungsten silicide starts from defining a field region for isolating devices, injecting ions for forming well diffusion regions and threshold voltage adjustment, and patterning a gate line. In the gate line patterning, a gate oxide film is formed on a substrate, and polysilicon, tungsten (or tungsten silicide) and cap gate layers are stacked in succession on the oxide film and patterned. Upon finishing the gate line patterning, an oxidation process is conducted for compensating for etch damages in the gate line patterning and the loss of gate oxide film.
Referring to FIG. 2a, the related art process for forming a metal line in a semiconductor device starts from defining a field region on a semiconductor substrate 21, forming a well region, injecting ions for adjusting Vt (not shown), and forming a gate oxide film 22. Then, a material layer for forming a gate, such as a polysilicon layer 23, is formed on the gate oxide film 22. And, as shown in FIG. 2b, a tungsten layer (or a tungsten silicide layer) 24 is formed on the polysilicon layer 23. As shown in FIG. 2c, a cap gate layer 25 is formed on the tungsten layer 24. And, as shown in FIG. 2d, the stack of the cap gate layer 25, the tungsten layer 24, the polysilicon layer 23 and the gate oxide film 22 is selectively etched, to form a gate electrode 26. As shown in FIG. 2e, an oxidation process is conducted for compensating for stresses applied to the substrate during the patterning of the gate electrode 26.
The oxidation process is conducted in an N.sub.2 /O.sub.2 ambient according to the following steps.
A wafer having passed through the gate line patterning process is loaded into a furnace or a RTP (Rapid Thermal Process) equipment, of which inside is at 500.about.700.degree. C. in a nitrogen gas. Upon finishing loading of the wafer, inside temperature of the equipment is elevated to a range of 800.about.900.degree. C. Annealing is conducted at 800.about.900.degree. C. in a nitrogen ambient, and then an oxidation is conducted. In this instance, in the oxidation process, N.sub.2 /O.sub.2 gas is introduced into the equipment while the 800.about.900.degree. C. is maintained. Upon completion of the oxidation process, the temperature inside of the equipment is lowered to 500.about.700.degree. C. and the O.sub.2 gas is cut off. If the oxidation process proceeds without taking into account the phenomenon that the tungsten or tungsten silicide layer is liable to oxidize in the oxidation, the electrical characteristics of the gate line itself may be deteriorated. The easy oxidization of W in the W or WSIX layer during the oxidation process forms many protruded portions at the sides of the gate line, which deteriorate the electrical characteristics of the gate line as well as a withstand voltage of the gate oxide film. The abnormal oxidation of the W or WSix layer also occurs after patterning of bit line of W or WSix layer or metal line.
Accordingly, the aforementioned related art method for forming a metal line has the following problems.
When heat treatment is conducted using the furnace, abnormal oxidation occurs because the tungsten or tungsten silicide is liable to oxidize due to the oxygen entered during loading of the wafer or during elevation of an inside temperature of the furnace. Though the oxygen entering into the furnace may be purged by nitrogen gas during the temperature elevation, the abnormal oxidation of the tungsten or tungsten silicide layer still cannot be prevented because oxygen is used in the oxidation process. This abnormal oxidation of the tungsten or tungsten silicide layer also occurrs when heat treatment is conducted using RTP equipment, and deterioration of metal line characteristics can not be prevented. When such an abnormal oxidation occurs, many protruded portions form at the sides of the metal line, which deteriorates not only electrical characteristics of the metal line itself, but also a withstand voltage of a gate oxide film if the metal line is a gate line. This abnormal oxidation occurred is concentrated at 1 part in FIG. 2e.